FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
Jeff Zhang, Siddharth Garg

TL;DR
FATE is a novel framework that significantly accelerates timing error prediction in DNN accelerators, enabling efficient architectural exploration with high accuracy and reduced simulation time.
Contribution
FATE introduces DelayNet and a statistical sampling method to achieve fast, accurate timing simulations for DNN hardware, reducing simulation time by up to 58 times.
Findings
FATE achieves 8-58x speed-up in timing simulations with less than 2% error.
SMR implementation yields 18% more energy savings than 2's complement at same accuracy.
FATE enables efficient comparison of different DNN hardware architectures.
Abstract
Deep neural networks (DNN) are increasingly being accelerated on application-specific hardware such as the Google TPU designed especially for deep learning. Timing speculation is a promising approach to further increase the energy efficiency of DNN accelerators. Architectural exploration for timing speculation requires detailed gate-level timing simulations that can be time-consuming for large DNNs that execute millions of multiply-and-accumulate (MAC) operations. In this paper we propose FATE, a new methodology for fast and accurate timing simulations of DNN accelerators like the Google TPU. FATE proposes two novel ideas: (i) DelayNet, a DNN based timing model for MAC units; and (ii) a statistical sampling methodology that reduces the number of MAC operations for which timing simulations are performed. We show that FATE results in between 8 times-58 times speed-up in timing…
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Taxonomy
TopicsEnergy Harvesting in Wireless Networks · Opportunistic and Delay-Tolerant Networks · Particle Detector Development and Performance
