A tunnel FET compact model including non-idealities with verilogy implementation

TL;DR

This paper introduces a comprehensive compact model for Tunnel FETs that includes non-idealities like trap-assisted tunneling and band edge effects, implemented in Verilog-A for circuit simulation and device analysis.

Contribution

The model uniquely incorporates non-idealities such as TAT and Urbach tail effects, providing a tool for accurate device physics representation and circuit simulation.

Findings

Model captures key non-idealities affecting TFET performance.

Closed-form expressions enable accurate physics-based analysis.

Model validated against experimental data.

Abstract

We present a compact model for Tunnel Field Effect Transistors (TFET), that captures sev- eral non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps (Dit), along with Verilog-A implementation. We show that the TAT, together with band edge non-abruptness known as the Urbach tail, sets the lower limit of the sub-threshold swing and the minimum achievable current at a given temperature. Presence of charged trap states also contributes to reduced gate efficiency. We show that we can decouple the contribution of each of these processes and extract the intrinsic sub-threshold swing from a given experimental data. We derive closed form expressions of channel potential, electric field and effective tunnel energy window to accurately capture the essential device physics of TFETs. We test the model against recently published exper- imental data, and simulate simple TFET circuits using the Verilog-A model. The compact model provides a framework for TFET technology projections with improved device metrics such as better electrostatic design, reduced TAT, material with better transport properties etc.