A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes

TL;DR

This paper presents a low-latency, high-throughput implementation of list successive-cancellation decoding for polar codes, using selective expansion and double thresholding to reduce complexity and delay.

Contribution

It introduces a novel low-latency LSCD architecture with selective expansion and double thresholding, optimized for large list sizes in polar codes.

Findings

Achieves 460 Mbps decoding throughput at 658 MHz.

Effective reduction in latency for large list sizes.

Demonstrates practical VLSI implementation in 90 nm CMOS.

Abstract

Due to their provably capacity-achieving performance, polar codes have attracted a lot of research interest recently. For a good error-correcting performance, list successive-cancellation decoding (LSCD) with large list size is used to decode polar codes. However, as the complexity and delay of the list management operation rapidly increase with the list size, the overall latency of LSCD becomes large and limits the applicability of polar codes in high-throughput and latency-sensitive applications. Therefore, in this work, the low-latency implementation for LSCD with large list size is studied. Specifically, at the system level, a selective expansion method is proposed such that some of the reliable bits are not expanded to reduce the computation and latency. At the algorithmic level, a double thresholding scheme is proposed as a fast approximate-sorting method for the list management operation to reduce the LSCD latency for large list size. A VLSI architecture of the LSCD implementing the selective expansion and double thresholding scheme is then developed, and implemented using a UMC 90 nm CMOS technology. Experimental results show that, even for a large list size of 16, the proposed LSCD achieves a decoding throughput of 460 Mbps at a clock frequency of 658 MHz.