Radiation-Tolerant, High-speed Serial Link Design with SRAM-based FPGAs

TL;DR

This paper presents a radiation-tolerant, high-speed serial link design implemented on SRAM-based FPGAs, employing various mitigation techniques to ensure reliable data transmission in high-radiation environments like high energy physics experiments.

Contribution

It introduces a novel bi-directional serial link with adaptive error correction and redundancy techniques for radiation environments, enhancing FPGA reliability.

Findings

Achieved 6.25 Gbps data rate with error correction

Demonstrated improved fault tolerance through interleaving and modular redundancy

Validated system performance via fault injection tests

Abstract

High-speed serial links implemented in SRAM-based FPGAs have been extensively used in the trigger and data acquisition systems of High Energy Physics experiments. Usually, their application has been restricted to off-detector, mostly due the sensitivity of SRAM-based FPGA to radiation faults (single event upsets). However, the device tolerance to radiation environments can be achieved by adopting dedicated mitigation techniques such as information redundancy, hardware redundancy and configuration scrubbing. In this work, we discuss the design of a bi-directional serial link running at 6.25 Gbps based on a Xilinx Kintex-7 FPGA. The link is protected against single event upsets by means of all the above-mentioned methods. A self-synchronizing scrambler is used for DC-balance and data randomization, while the subsequent Reed-Solomon encoder/decoder detects and corrects bursts of errors in the transmitted data. The error correction capability of the line code is further increased by adopting the interleaving technique. Besides, in order to completely take advantage of available bandwidth and to cope with different rates of radiation-induced faults, the link can modulate the protection level of the Reed-Solomon code. The reliability of the link is also improved by means of modular redundancy on the frame alignment block. Besides, on the same FPGA, a scrubber repairs corrupted configuration frames in real-time. We present the test results carried out using the fault injection method. We show the performance of the link in terms of mean time between failures (MTBF) and fault tolerance to upsets.