On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

TL;DR

This paper investigates the fault resilience of RTL-based neural network accelerators, characterizing vulnerabilities and proposing a mitigation technique that improves fault correction efficiency by nearly 50%.

Contribution

It provides a detailed fault characterization of RTL NN accelerators and introduces a low-overhead mitigation method that outperforms existing solutions.

Findings

Fault severity depends on application and architectural factors.

Characterization reveals specific vulnerabilities in RTL NN components.

Proposed mitigation improves fault correction by 47.3% over state-of-the-art.

Abstract

Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute- and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular, fault characterization and mitigation. By following a High-Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.