The Phase-1 Upgrade for the Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC

TL;DR

This paper presents the design and testing of a new interface board for the ATLAS Level-1 Muon Barrel Trigger upgrade, enhancing data transfer and trigger algorithm capabilities using FPGA technology.

Contribution

It introduces the first prototype of a new Barrel Interface Board with FPGA, supporting optical data transmission and advanced trigger algorithms for the ATLAS experiment.

Findings

Successful hardware implementation demonstrated

Passed initial functional tests

Validated integration with existing systems

Abstract

The Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC makes use of Resistive Plate Chamber (RPC) detectors. The on-detector trigger electronics modules are able to identify muons with predefined transverse momentum values (pT) by executing a coincidence logic on signals coming from the various detector layers. Then, on-detector trigger boards transfer trigger data to the off-detector electronics. A complex trigger system processes the incoming data by combining trigger information from the Barrel and the End-cap regions, and by providing the combined muon candidate to the Central Trigger Processor (CTP). For almost a decade, the Level-1 Trigger system has been operating very well, despite the challenging requirements on trigger efficiency and performance, and the continuously increasing LHC luminosity. In order to cope with these constraints, various upgrades for the full trigger system were already deployed, and others have been designed to be installed in the next years. Most of the upgrades to the trigger system rely on state-of-the-art technologies, thus allowing to increase the processing power and data transfer bandwidth, and to design more complex trigger menus. As a consequence, more trigger candidates might be selected by the system, thus supporting new physics studies or topological selections. In this work, we discuss the design of the first prototype of the new Barrel Interface Board, designed around a Xilinx FPGA, which will be used to transfer RPC trigger data to the CTP system. The main requirement for the board is to support the optical transmission of the trigger data with fixed latency and to allow the implementation of new trigger algorithms. We describe the hardware implementation and the results of the first functional and integration tests.