Experimental verification of electrostatic boundary conditions in gate-patterned quantum devices

TL;DR

This paper models electrostatic boundary conditions in gate-patterned quantum devices, demonstrating how accurate boundary modeling aligns with experimental results and enables precise device simulation.

Contribution

It introduces an improved electrostatic boundary condition model for gate-patterned quantum devices, validated by experimental data and applicable with standard simulation tools.

Findings

Best boundary condition match with experimental pinch-off data

Observation of quantised current driven by surface acoustic waves

Modeling sensitivity to back boundary conditions

Abstract

In a model of a gate-patterned quantum device it is important to choose the correct electrostatic boundary conditions (BCs) in order to match experiment. In this study, we model gated-patterned devices in doped and undoped GaAs heterostructures for a variety of BCs. The best match is obtained for an unconstrained surface between the gates, with a dielectric region above it and a frozen layer of surface charge, together with a very deep back boundary. Experimentally, we find a 0.2V offset in pinch-off characteristics of one-dimensional channels in a doped heterostructure before and after etching off a ZnO overlayer, as predicted by the model. Also, we observe a clear quantised current driven by a surface acoustic wave through a lateral induced n-i-n junction in an undoped heterostructure. In the model, the ability to pump electrons in this type of device is highly sensitive to the back BC. Using the improved boundary conditions, it is straightforward to model quantum devices quite accurately using standard software.