Physics-Inspired Optimization for Quadratic Unconstrained Problems Using a Digital Annealer
Maliheh Aramon, Gili Rosenberg, Elisabetta Valiante, Toshiyuki, Miyazawa, Hirotaka Tamura, Helmut G. Katzgraber

TL;DR
The paper presents the Fujitsu Digital Annealer, a hardware-accelerated solver for quadratic unconstrained binary optimization problems, demonstrating significant speedups over traditional algorithms for dense problems, with potential for larger problem sizes.
Contribution
It introduces a digital annealer with a novel parallel-trial scheme and dynamic escape mechanism, achieving substantial speedups and scalability improvements over existing methods.
Findings
Two orders of magnitude speedup for dense spin-glass problems
No speedup observed for sparse 2D problems, explained theoretically
Improved scaling for fully connected problems of moderate difficulty
Abstract
The Fujitsu Digital Annealer (DA) is designed to solve fully connected quadratic unconstrained binary optimization (QUBO) problems. It is implemented on application-specific CMOS hardware and currently solves problems of up to 1024 variables. The DA's algorithm is currently based on simulated annealing; however, it differs from it in its utilization of an efficient parallel-trial scheme and a dynamic escape mechanism. In addition, the DA exploits the massive parallelization that custom application-specific CMOS hardware allows. We compare the performance of the DA to simulated annealing and parallel tempering with isoenergetic cluster moves on two-dimensional and fully connected spin-glass problems with bimodal and Gaussian couplings. These represent the respective limits of sparse versus dense problems, as well as high-degeneracy versus low-degeneracy problems. Our results show that…
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