Energy Efficient Tri-State CNFET Ternary Logic Gates

TL;DR

This paper introduces a novel energy-efficient ternary logic circuit design using CNFETs, leveraging their unique properties to reduce power consumption and improve performance in multi-valued logic applications.

Contribution

The paper presents a new method for designing ternary logic circuits with CNFETs, including a 2-digit adder-subtractor and a power-efficient ternary ALU, validated through simulations.

Findings

Circuits operate correctly under PVT variations.

Proposed designs achieve power savings.

Successful simulation of complex ternary operations.

Abstract

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano devices are two feasible solutions to overcome these problems. In this paper, a novel method is presented to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, for example, adjusting the Carbon Nanontube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. In an effort to show a more detailed application of our approach, we design a 2-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, a power efficient ternary logic ALU has been design based on the proposed gates.