A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB

TL;DR

This paper presents an energy-efficient bitmap index creation core implemented in 65-nm SOTB CMOS technology, achieving low power consumption and high performance suitable for energy-sensitive systems.

Contribution

It introduces a 65-nm SOTB-based BIC chip with dual supply voltage operation, demonstrating significant power reduction in standby mode using reverse back-gate biasing.

Findings

Active mode consumes 162.9 pJ/cycle at 41 MHz

Standby power reduced to 10.6 μW with clock gating

Standby power further reduced to 2.64 nW with reverse back-gate biasing

Abstract

The ability to maximize the performance during peak workload hours and minimize the power consumption during off-peak time plays a significant role in the energy-efficient systems. Our previous work has proposed a high-performance multi-core bitmap index creator (BIC) in a field-programmable gate array that could deliver higher indexing throughput than central processing units and graphics processing units. This brief extends the previous study by focusing on the application-specific integrated circuit implementation of the proposed BIC in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process. The BIC chip can operate with different supply voltage from 0.4 V to 1.2 V. In the active mode with the supply voltage of 1.2 V, the BIC chip is fully operational at 41 MHz and consumes 162.9 pJ/cycle. In the standby mode with the supply voltage of 0.4 V and clock-gating technique, the power consumption was reduced to 10.6 uW. The standby power is also dramatically reduced to 2.64 nW due to the utilization of reverse back-gate biasing technique. This achievement is considerable importance to the energy-efficient systems.