Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh

TL;DR
This paper introduces a high-speed, digit-slicing based pipeline Radix-2 FFT architecture optimized for wireless communication systems, achieving significant speed improvements over traditional designs.
Contribution
It presents a novel digit-slicing multiplier-less Radix-2 FFT architecture that enhances speed and efficiency for high-performance wireless communication applications.
Findings
Achieved 669.277 MHz processing speed on FPGA
Reduced gate count to 14,854 gates
Significant performance improvement over Radix-2 DIF FFT
Abstract
The prevalent need for very high-speed digital signals processing in wireless communications has driven the communications system to high-performance levels. The objective of this paper is to propose a novel structure for efficient implementation for the Fast Fourier Transform (FFT) processor to meet the requirement for high-speed wireless communication system standards. Based on the algorithm, architecture analysis, the design of pipeline Radix 2power of 2 SDF FFT processor based on digit-slicing Multiplier-Less is proposed. Furthermore, this paper proposed an optimal constant multiplication arithmetic design to multiply a fixed point input selectively by one of the several present twiddle factor constants. The proposed architecture was simulated using MATLAB software and the Field Programmable Gate Array (FPGA) Virtex 4 was targeted to synthesis the proposed architecture. The design…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
