Design a TDC in SiGe for RPC's electronics Front-end for the use in a high-rate experiment

TL;DR

This paper presents the design and initial testing of a silicon-germanium (SiGe) based TDC for RPC detector front-end electronics, emphasizing high speed, low power, and radiation hardness for high-rate experiments.

Contribution

It introduces a novel SiGe TDC prototype with a local oscillator up to 3 GHz, achieving 15 ps jitter and optimized data transmission for high-rate RPC applications.

Findings

TDC prototype achieves 15 ps jitter.

Oscillation frequency range of 0.6 to 3 GHz.

Binary data output enables efficient data processing.

Abstract

With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain is made up of an amplifier, a discriminator, a TDC. The new front-end is realized with the use of silicon-germanium (SiGe) components, provided by IHP microelectronics. With this technology we can implement BJT and CMOS transistors on the same chip. The benefit of this improvement is to minimize: power consumption of the channels ($2 \div 3$ $ \frac{mW}{ch}$), noise (500 $e^-$ r.m.s), radiation hardness (10 kGy,$10^3$ $\frac{n}{cm}$) and it maximizes the speed of response electronics. In this work I will highlight the first TDC prototypes' results. The TDC uses a local oscillator, that has an oscillation range between $0.6 \div 3 $ GHz, and a the temporal jitter of 15 ps. The data output from the TDC are presented in binary in order to lighten data processing to the acquisition system. Moreover, we are studying a way to minimize system latency. This optimization involves the addition of a serializer (PISO) that sends the TDC data output to the acquisition system at 2 GHz.