Scanning Test System Prototype of p/sFEB for the ATLAS Phase-I sTGC Trigger Upgrade

TL;DR

This paper presents a prototype scanning test system for the p/sFEB boards used in the ATLAS sTGC trigger upgrade, enabling performance verification through simulated signals and integrated software-hardware testing.

Contribution

The paper introduces a novel scanning test system prototype specifically designed for p/sFEB boards, enhancing testing accuracy for the ATLAS sTGC upgrade.

Findings

Successful simulation signal generation for testing

Effective cooperation between PC software and FPGA XADC

Validated performance of the test system prototype

Abstract

The Pad Front End Board (pFEB) and the Strip Front End Board (sFEB) are developed for the ATLAS Phase-I sTGC Trigger Upgrade. The pFEB is used to to gather and analyze pads trigger, and the sFEB is developed to accept the pad trigger to define the regions-of-interest for strips readout. The performance of p/sFEBs must be confirmed before they are mounted on the sTGC detector. We will present the scanning test system prototype which is designed according to the test requirements of the p/sFEB. In this test system prototype, a simulation signal board is developed to generate different types of signal to the p/sFEB. PC software and FPGA XADC cooperate to achieve the scan test of analog parameter.