Scalable Platform for Adaptive optics Real-time Control (SPARC) Part 1: Concept, Architecture and Validation

TL;DR

This paper presents SPARC, a scalable FPGA-based architecture for real-time adaptive optics control, demonstrating its effectiveness through hardware and simulation tests on an affordable development board, suitable for various AO scenarios.

Contribution

Introduction of a novel, scalable FPGA architecture for adaptive optics real-time control, validated with hardware and simulation results on an inexpensive platform.

Findings

Median AO reconstruction time of 39.4us for 11x11 subapertures

Reconstruction time increases to 1.283 ms for 50x50 subapertures

Latency mainly affected by DDR memory access time

Abstract

We demonstrate a novel architecture for Adaptive Optics (AO) control based on FPGAs (Field Programmable Gate Arrays), making active use of their configurable parallel processing capability. SPARC's unique capabilities are demonstrated through an implementation on an off-the-shelf inexpensive Xilinx VC-709 development board. The architecture makes SPARC a generic and powerful Real-time Control (RTC) kernel for a broad spectrum of AO scenarios. SPARC is scalable across different numbers of subapertures and pixels per subaperture. The overall concept, objectives, architecture, validation and results from simulation as well as hardware tests are presented here. For Shack-Hartmann wavefront sensors, the total AO reconstruction time ranges from a median of 39.4us (11x11 subapertures) to 1.283 ms (50x50 subapertures) on the development board. For large wavefront sensors, the latency is dominated by access time (~1 ms) of the standard DDR memory available on the board. This paper is divided into two parts. Part 1 is targeted at astronomers interested in the capability of the current hardware. Part 2 explains the FPGA implementation of the wavefront processing unit, the reconstruction algorithm and the hardware interfaces of the platform. Part 2 mainly targets the embedded developers interested in the hardware implementation of SPARC.