Development of next generation LLRF control system for J-PARC rapid cycling synchrotron

TL;DR

This paper describes the development of a new MicroTCA.4 based LLRF control system for J-PARC's RCS, replacing outdated hardware to improve maintainability and performance in high-intensity proton beam acceleration.

Contribution

The paper introduces a modern MicroTCA.4 based LLRF control system with enhanced communication and control capabilities for the J-PARC RCS, replacing obsolete VME-based hardware.

Findings

Successful implementation of the new system configuration

Preliminary tests show promising control performance

Enhanced data transfer simplifies system architecture

Abstract

The low level rf (LLRF) control system for the rapid cycling synchrotron (RCS) of the Japan Proton Accelerator Research Complex (J-PARC) started its operation in 2007. The key functions of the LLRF control system are the dual harmonic auto voltage control, which generates superposed voltages of the fundamental accelerating harmonic and the second harmonic in a single wideband magnetic alloy (MA) cavity, and the multiharmonic rf feedforward to compensate the beam loading in the MA cavity caused by high intensity beams. These functions are necessary to accelerate high intensity proton beams. The system has been working well without major problems for more than ten years. However, the old FPGAs (Xilinx Virtex-II pro etc.) are discontinued and not supported by the current development environment. It will be difficult to maintain the system in near future. Thus, we are planning to replace the existing VME-based LLRF control system with a new MicroTCA.4 based system. The system controls twelve cavities independently and calculates vector sum of the cavity voltages in real time for phase feedback. Signal and data transfer between the modules is a key to realize the functions. In the existing system, the transfer is implemented not only the backplane but also serial link via cables between the VME modules. It is much more simplified in the new system thanks to the high speed communication capability of the MicroTCA.4 backplane. In this article, we describe the configuration of the system under development, the implemented functions, and preliminary test results.