Mitigating Wordline Crosstalk using Adaptive Trees of Counters

TL;DR

This paper introduces a Counter-based Adaptive Tree (CAT) method to effectively mitigate wordline crosstalk in DRAM by dynamically allocating counters based on access patterns, reducing refresh power and performance overhead.

Contribution

The paper proposes a novel adaptive tree of counters approach that improves crosstalk mitigation efficiency while reducing hardware and power overhead compared to existing methods.

Findings

CAT reduces refresh power overhead to 7%.

CAT incurs only 0.5% performance overhead.

Hardware synthesis shows low area overhead for CAT.

Abstract

High access frequency of certain rows in the DRAM may cause data loss in cells of physically adjacent rows due to crosstalk. The malicious exploit of this crosstalk by repeatedly accessing a row to induce this effect is known as row hammering. Additionally, inadvertent row hammering may also occur due to the natural weighted nature of applications' access patterns. In this paper, we analyze the efficiency of existing approaches for mitigating wordline crosstalk and demonstrate that they have been conservatively designed. Given the unbalanced nature of DRAM accesses, a small group of dynamically allocated counters in banks can deterministically detect hot rows and mitigate crosstalk. Based on our findings, we propose a Counter-based Adaptive Tree (CAT) approach to mitigate wordline crosstalk using adaptive trees of counters to guide appropriate refreshing of vulnerable rows. The key idea is to tune the distribution of the counters to the rows in a bank based on the memory reference patterns. In contrast to deterministic solutions, CAT utilizes fewer counters, making it practically feasible to be implemented on-chip. Compared to existing probabilistic approaches, CAT more precisely refreshes rows vulnerable to crosstalk based on their access frequency. Experimental results on workloads from four benchmark suites show that CAT reduces the Crosstalk Mitigation Refresh Power Overhead in quad-core systems to 7%, which is an improvement over the 21% and 18% incurred in the leading deterministic and probabilistic approaches, respectively. Moreover, CAT incurs very low performance overhead (0.5%). Hardware synthesis evaluation shows that CAT can be implemented on-chip with only a nominal area overhead.