Design of CMOS-memristor Circuits for LSTM architecture

TL;DR

This paper presents a CMOS-memristor hardware architecture for LSTM neural networks aimed at near-sensor processing, validated through a forecasting application, addressing challenges of parallelism and complexity.

Contribution

It introduces a novel 0.18 μm CMOS-GST memristor LSTM hardware design for efficient near-sensor processing.

Findings

Successful validation in a forecasting task

Demonstrates feasibility of CMOS-memristor LSTM hardware

Addresses parallelism and complexity challenges in near-sensor LSTM

Abstract

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.