Study of Full Parallel RS(31,27) Encoder for a 3.2 Gbps Serial Transmitter in 0.18 um CMOS Technology

TL;DR

This paper introduces a high-speed, full parallel RS(31,27) encoder for a 3.2 Gbps serial transmitter, optimized for stability and implemented on FPGA, enabling effective error correction in high-speed communication.

Contribution

It presents a novel full parallel RS(31,27) encoder design optimized for high speed and stability in CMOS technology, suitable for 3.2 Gbps serial transmission.

Findings

Achieved 3.2 Gbps data rate with the proposed encoder.

Successfully implemented on FPGA with stable performance.

Corrects up to 20 bits of consecutive errors.

Abstract

This work presents the design of an RS(31,27) Reed Solomon encoder for a 3.2 Gbps serial transmitter in 0.18 um CMOS technology. The proposed encoder is designed with a novel full parallel structure optimized for high speed and high stability. One data frame contains 2 interleaved RS(31,27) codes and thus it can correct at most 20 bits of consecutive errors. A corresponding decoder is implemented on Xilinx Kintex-7 FPGA.