Accelerating CNN inference on FPGAs: A Survey

TL;DR

This survey reviews recent FPGA-based CNN inference accelerators, analyzing their architectures, optimizations, and performance, highlighting trends and future directions in hardware deep learning acceleration.

Contribution

It provides a comprehensive overview of recent FPGA CNN acceleration methods, comparing various optimization techniques and identifying key research trends.

Findings

FPGAs are well-suited for CNN workloads due to their reconfigurability.

Recent methods improve performance through convolutional and memory optimizations.

State-of-the-art approaches demonstrate significant speedups in CNN inference on FPGAs.

Abstract

Convolutional Neural Networks (CNNs) are currently adopted to solve an ever greater number of problems, ranging from speech recognition to image classification and segmentation. The large amount of processing required by CNNs calls for dedicated and tailored hardware support methods. Moreover, CNN workloads have a streaming nature, well suited to reconfigurable hardware architectures such as FPGAs. The amount and diversity of research on the subject of CNN FPGA acceleration within the last 3 years demonstrates the tremendous industrial and academic interest. This paper presents a state-of-the-art of CNN inference accelerators over FPGAs. The computational workloads, their parallelism and the involved memory accesses are analyzed. At the level of neurons, optimizations of the convolutional and fully connected layers are explained and the performances of the different methods compared. At the network level, approximate computing and datapath optimization methods are covered and state-of-the-art approaches compared. The methods and tools investigated in this survey represent the recent trends in FPGA CNN inference accelerators and will fuel the future advances on efficient hardware deep learning.