Stability Analysis for Fast Settling Switched DPLL

TL;DR

This paper presents a stability analysis for fast settling switched DPLL architectures using Multiple Lyapunov Functions, leading to a CMOS-fabricated 5GHz fractional-N DPLL with record lock time.

Contribution

It introduces a stability condition framework for switched DPLLs using MLFs, enabling fast settling times without chattering, validated through a fabricated CMOS DPLL.

Findings

Achieved a 1us settling time in a 5GHz fractional-N DPLL

Validated stability conditions with a record lock time for fractional-N DPLLs

Ensured no chattering during subsystem switching

Abstract

In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to achieve better lock time and jitter performance. This work derives stability conditions for such DPLL architectures using Multiple Lyapunov Functions (MLFs) for switched systems. The loop-parameters chosen on the basis of these stability conditions ensure that chattering phenomenon does not occur during switching between different subsystems. A 5GHz fractional-N DPLL designed with these loop-parameter values is fabricated in CMOS65nm-LL technology. The measured settling time of the implemented DPLL is within 1us. The efficiency of switching rule and stability conditions used for this DPLL is validated with the fast settling response, which is the best lock time reported until now for fractional-N DPLLs.