Hardware Transactional Persistent Memory

TL;DR

This paper presents a novel software protocol combined with a Persistent Memory Controller that enables correct and atomic ordering of Hardware Transactional Memory transactions on Persistent Memory, improving performance without hardware changes.

Contribution

It introduces a new software protocol and hardware support for atomic, ordered HTM transactions on Persistent Memory without requiring processor microarchitecture modifications.

Findings

Comparable performance to standard HTM transactions on volatile memory

Significant throughput and latency improvements over persistent transactional locking

Effective ordering and atomicity achieved with the proposed approach

Abstract

Emerging Persistent Memory technologies (also PM, Non-Volatile DIMMs, Storage Class Memory or SCM) hold tremendous promise for accelerating popular data-management applications like in-memory databases. However, programmers now need to deal with ensuring the atomicity of transactions on Persistent Memory resident data and maintaining consistency between the order in which processors perform stores and that in which the updated values become durable. The problem is specially challenging when high-performance isolation mechanisms like Hardware Transactional Memory (HTM) are used for concurrency control. This work shows how HTM transactions can be ordered correctly and atomically into PM by the use of a novel software protocol combined with a Persistent Memory Controller, without requiring changes to processor cache hardware or HTM protocols. In contrast, previous approaches require significant changes to existing processor microarchitectures. Our approach, evaluated using both micro-benchmarks and the STAMP suite compares well with standard (volatile) HTM transactions. It also yields significant gains in throughput and latency in comparison with persistent transactional locking.