An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter

TL;DR

This paper improves the decimation process in oversampling systems by designing and implementing a fast CIC filter with associated filters, focusing on speed, power, and silicon area efficiency for FPGA deployment.

Contribution

It presents a novel design and VLSI implementation of an enhanced CIC decimation filter with associated half-band filters and droop correction, optimized for FPGA.

Findings

Achieved faster decimation with reduced power consumption.

Successfully implemented on Virtex II FPGA.

Demonstrated trade-offs between speed, power, and silicon area.

Abstract

The oversampling technique has been shown to increase the SNR and is used in many high-performance systems such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and it's VLSI implementation which is the sub-component in the oversampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half-band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded into Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.