A 5.5 ps Time-interval RMS Precision Time-to-Digital Convertor Implemented in Intel Arria 10 FPGA

TL;DR

This paper demonstrates a high-precision 5.5 ps RMS time-to-digital converter implemented in Intel Arria 10 FPGA, utilizing a tapped delay line structure and parallel TDLs to achieve excellent timing resolution.

Contribution

The paper introduces a novel TDC design in Intel Arria 10 FPGA using parallel TDLs and an ones counter encoding scheme for enhanced timing precision.

Findings

Achieved 5.45 ps RMS precision in time-interval measurements

Successfully implemented high-performance TDC in mainstream Intel FPGA

Validated the delay chain characteristics with FPGA logic resources

Abstract

As an important part of the field programmable gate array (FPGA) market, Intel FPGA has also great potential for implementation of time-to-digital convertor (TDC). In this paper, the basic tapped delay line (TDL) TDC structure is adapted in Intel Arria 10 FPGA, which is manufactured with 20 nm process technology. Because of the serious bubble problem for FPGA made by state-of-art process, the ones counter encoding scheme is employed to maintain the delay elements in TDL resolvable for achieving high TDC time precision. The test of TDC bin width reveals that the characteristics of the delay chain are highly consistent with the fundamental structure of logic resource in the FPGA. To improve TDC time precision, four TDLs are combined parallel for final TDC implementation. Using two identical TDC channels, the average RMS precision for measurements of time-intervals in the range from 0 to 50 ns reaches 5.45 ps. The test results demonstrate that high performance TDC can be implemented in current Intel main-stream FPGAs as well.