Standard Cell Library Evaluation with Multiple lithography-compliant verification and Improved Synopsys Pin Access Checking Utility
Yongfu Li, Wan Chia Ang, Chin Hui Lee, Kok Peng Chua, Yoong Seang, Jonathan Ong, Chiu Wing Colin Hui

TL;DR
This paper presents enhancements to the Synopsys PAC methodology for evaluating standard cell layouts, improving pin accessibility checks, design rule compliance, and printability verification to streamline physical layout design.
Contribution
It introduces multiple improvements to the PAC methodology, including reducing test cell count, increasing pin connection complexity, and integrating additional verification constraints.
Findings
Reduced number of test cells needed for each abutment condition
Enhanced pin connection complexity for better accessibility evaluation
Integrated physical verification methods for rule compliance and printability
Abstract
While standard cell layouts are drawn with minimum design rules to maximize the benefit of design area shrinkage, the complicated design rules have caused difficulties with signal routes accessing the pins in standard cell layouts. As a result, it has become a great challenge for physical layout designers to design a standard cell layout that is optimized for area, power, timing, signal integrity, and printability. Multiple design iterations are required to consider pin accessibility during standard cells layout to increase the number of feasible solutions available to the router. In this work, we will demonstrate several improvements with the Synopsys PAC methodology, such as reducing the number of cells required for each Synopsys 'testcell' with the same cell abutment condition, increasing the complexity of the pin connection for better pin accessibility evaluation. We also recommend…
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Taxonomy
TopicsAdvancements in Photolithography Techniques · VLSI and Analog Circuit Testing · VLSI and FPGA Design Techniques
