Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures

TL;DR

This paper presents a comprehensive mapping process for lattice surgery-based quantum circuits on surface code architectures, highlighting efficiency trade-offs between checkerboard and tile-based designs to optimize resource use and reduce overhead.

Contribution

It introduces a full mapping methodology for quantum circuits on surface code architectures, comparing two layouts and analyzing their resource and communication efficiencies.

Findings

Checkerboard architecture is 2x more qubit-efficient.

Tile-based architecture reduces communication overhead by up to 86%.

Tile-based architecture lowers latency overhead by up to 79%.

Abstract

Quantum error correction (QEC) and fault-tolerant (FT) mechanisms are essential for reliable quantum computing. However, QEC considerably increases the computation size up to four orders of magnitude. Moreover, FT implementation has specific requirements on qubit layouts, causing both resource and time overhead. Reducing spatial-temporal costs becomes critical since it is beneficial to decrease the failure rate of quantum computation. To this purpose, scalable qubit plane architectures and efficient mapping passes including placement and routing of qubits as well as scheduling of operations are needed. This paper proposes a full mapping process to execute lattice surgery-based quantum circuits on two surface code architectures, namely a checkerboard and a tile-based one. We show that the checkerboard architecture is 2x qubit-efficient but the tile-based one requires lower communication overhead in terms of both operation overhead (up to 86%) and latency overhead (up to 79%).