Multiple-Lithography-Compliant Verification for Standard Cell Library Development Flow

TL;DR

This paper presents an integrated verification flow for ensuring standard cell libraries meet full lithography compliance, addressing challenges in design rule, manufacturability, and patterning constraints, especially for abutted cells.

Contribution

It introduces a comprehensive lithography-compliant verification method and an area-efficient placement technique for standard cell libraries, filling a gap in existing tools.

Findings

Developed a unified lithography verification flow.

Validated the approach with standard cell placement experiments.

Enhanced the manufacturability and compliance of standard cell libraries.

Abstract

Starting from 22-nm, a standard cell must be designed to be full lithography-compliant, which includes Design Rule Check, Design-for-Manufacturability and Double-Patterning compliant. It has become a great challenge for physical layout designers to provide a full lithography-compliant standard cell layout that is optimized for area, power, timing, signal integrity, and yield. This challenge is further exacerbated with abutted single- and multiple-height standard cells. At present, different foundries and library vendors have different approaches for full lithography-compliant library preparation and validation. To the best of our knowledge, there is no single tool integrates all types of lithography-compliant check in standard cell libraries validation flow. In this work, we will demonstrate multiple lithography-compliant verification for standard cell library development flow. Validation flow and detailed algorithm implementation will be explained to assist engineers to achieve full lithography-compliant standard cell libraries. An area-efficient standard cell placement methodology will also be discussed to validate the issues arises from standard cell abutment.