f-CNN$^{\text{x}}$: A Toolflow for Mapping Multi-CNN Applications on FPGAs

TL;DR

f-CNN$^{ ext{x}}$ is an automated FPGA toolflow that efficiently maps multiple CNNs, optimizing resource allocation and scheduling to enhance performance and power efficiency in latency-sensitive applications.

Contribution

The paper introduces a novel multi-CNN FPGA architecture and an automated design space exploration method with a scheduling algorithm for improved multi-CNN mapping.

Findings

Up to 50% performance improvement over contention-unaware FPGA mappings.

Up to 6.8x higher performance-per-Watt compared to optimized GPUs.

Effective resource and bandwidth management for multiple CNNs on FPGAs.

Abstract

The predictive power of Convolutional Neural Networks (CNNs) has been an integral factor for emerging latency-sensitive applications, such as autonomous drones and vehicles. Such systems employ multiple CNNs, each one trained for a particular task. The efficient mapping of multiple CNNs on a single FPGA device is a challenging task as the allocation of compute resources and external memory bandwidth needs to be optimised at design time. This paper proposes f-CNN$^{\text{x}}$, an automated toolflow for the optimised mapping of multiple CNNs on FPGAs, comprising a novel multi-CNN hardware architecture together with an automated design space exploration method that considers the user-specified performance requirements for each model to allocate compute resources and generate a synthesisable accelerator. Moreover, f-CNN$^{\text{x}}$ employs a novel scheduling algorithm that alleviates the limitations of the memory bandwidth contention between CNNs and sustains the high utilisation of the architecture. Experimental evaluation shows that f-CNN$^{\text{x}}$'s designs outperform contention-unaware FPGA mappings by up to 50% and deliver up to 6.8x higher performance-per-Watt over highly optimised GPU designs for multi-CNN systems.