BLASYS: Approximate Logic Synthesis Using Boolean Matrix Factorization

TL;DR

This paper introduces BLASYS, a novel approximate logic synthesis method using Boolean matrix factorization, enabling controllable trade-offs between accuracy and circuit complexity, with significant power savings demonstrated.

Contribution

The paper presents a new approximate circuit synthesis approach using Boolean matrix factorization, including a scalable decomposition and exploration technique for large circuits.

Findings

Achieves up to 63% power savings.

Introduces an average relative error of 5%.

Outperforms previous Boolean circuit synthesis methods.

Abstract

Approximate computing is an emerging paradigm where design accuracy can be traded off for benefits in design metrics such as design area, power consumption or circuit complexity. In this work, we present a novel paradigm to synthesize approximate circuits using Boolean matrix factorization (BMF). In our methodology the truth table of a sub-circuit of the design is approximated using BMF to a controllable approximation degree, and the results of the factorization are used to synthesize a less complex subcircuit. To scale our technique to large circuits, we devise a circuit decomposition method and a subcircuit design-space exploration technique to identify the best order for subcircuit approximations. Our method leads to a smooth trade-off between accuracy and full circuit complexity as measured by design area and power consumption. Using an industrial strength design flow, we extensively evaluate our methodology on a number of testcases, where we demonstrate that the proposed methodology can achieve up to 63% in power savings, while introducing an average relative error of 5%. We also compare our work to previous works in Boolean circuit synthesis and demonstrate significant improvements in design metrics for same accuracy targets.