Fidelity benchmarks for two-qubit gates in silicon
W. Huang, C. H. Yang, K. W. Chan, T. Tanttu, B. Hensen, R. C. C. Leon,, M. A. Fogarty, J. C. C. Hwang, F. E. Hudson, K. M. Itoh, A. Morello, A., Laucht, A. S. Dzurak

TL;DR
This paper benchmarks two-qubit gate fidelities in silicon quantum dot qubits, demonstrating high fidelities with randomized benchmarking and identifying pathways to further improve gate performance.
Contribution
It provides the first rigorous randomized benchmarking of two-qubit gates in silicon quantum dots, establishing fidelity benchmarks and analyzing limiting factors.
Findings
Two-qubit Clifford gate fidelity of 94.7%
CROT gate fidelity of 98.0%
Fidelities limited by gate times relative to decoherence
Abstract
Universal quantum computation will require qubit technology based on a scalable platform, together with quantum error correction protocols that place strict limits on the maximum infidelities for one- and two-qubit gate operations. While a variety of qubit systems have shown high fidelities at the one-qubit level, superconductor technologies have been the only solid-state qubits manufactured via standard lithographic techniques which have demonstrated two-qubit fidelities near the fault-tolerant threshold. Silicon-based quantum dot qubits are also amenable to large-scale manufacture and can achieve high single-qubit gate fidelities (exceeding 99.9%) using isotopically enriched silicon. However, while two-qubit gates have been demonstrated in silicon, it has not yet been possible to rigorously assess their fidelities using randomized benchmarking, since this requires sequences of…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
