An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes

TL;DR

This paper presents low-complexity FPGA architectures for list successive cancellation decoding of polar codes with large list sizes, achieving high throughput and efficient resource usage.

Contribution

It introduces two novel low-complexity decoding schemes and FPGA architectures for LSCD with large list sizes, enabling practical high-speed polar code decoding.

Findings

Decodes 4096-bit polar code within 150 microseconds at 27 Mbps

Supports list size of 32 with reduced hardware complexity

Achieves efficient FPGA implementation of LSCD for polar codes

Abstract

Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 us, achieving a throughput of 27Mbps