Hierarchical Temporal Memory using Memristor Networks: A Survey

TL;DR

This survey reviews memristor-based hardware implementations of Hierarchical Temporal Memory, highlighting recent advances, advantages over digital solutions, and discussing current limitations and open challenges in the field.

Contribution

It provides a comprehensive overview of memristive HTM hardware designs, comparing analog, digital, and mixed-signal approaches, and discusses future research directions.

Findings

Memristive HTM offers faster processing and lower power consumption.

Analog memristive circuits outperform digital implementations in key metrics.

Current challenges include scalability, device reliability, and circuit integration issues.

Abstract

This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed.