A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder with Large List Size

TL;DR

This paper presents a high-throughput VLSI architecture for list successive cancellation decoding of polar codes with large list sizes, achieving over 800 Mbps throughput with optimized algorithms and hardware design.

Contribution

It introduces novel decoding schemes and a hardware architecture that significantly improve the throughput of LSCD for polar codes with large list sizes.

Findings

Achieves over 1 Gbps throughput for list size 8.

Provides efficient algorithms reducing decoding latency.

Demonstrates hardware implementation on 90 nm CMOS technology.

Abstract

As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted much research interest recently. Compared with other popular FEC codes, polar codes decoded by list successive cancellation decoding (LSCD) with a large list size have better error correction performance. However, due to the serial decoding nature of LSCD and the high complexity of list management (LM), the decoding latency is high, which limits the usage of polar codes in practical applications that require low latency and high throughput. In this work, we study the high-throughput implementation of LSCD with a large list size. Specifically, at the algorithmic level, to achieve a low decoding latency with moderate hardware complexity, two decoding schemes, a multi-bit double thresholding scheme and a partial G-node look-ahead scheme, are proposed. Then, a high-throughput VLSI architecture implementing the proposed algorithms is developed with optimizations on different computation modules. From the implementation results on UMC 90 nm CMOS technology, the proposed architecture achieves decoding throughputs of 1.103 Gbps, 977 Mbps and 827 Mbps when the list sizes are 8, 16 and 32, respectively.