On the Validity and Applicability of Models of Negative Capacitance and Implications for MOS Applications
J. A. Kittl, B. Obradovic, D. Reddy, T. Rakshit, R. M. Hatcher, and M., S. Rodder

TL;DR
This paper critically examines models of negative capacitance in ferroelectric MOSFETs, highlighting unphysical assumptions and proposing a clarified model that explains observed effects without implying true negative capacitance, impacting device applications.
Contribution
It provides a thorough analysis of negative capacitance models, identifies unphysical assumptions, and proposes a realistic model clarifying conditions for apparent negative capacitance in ferroelectric-dielectric stacks.
Findings
QS negative capacitance is unlikely in series capacitor models.
Strong interface coupling is necessary for apparent NC effects.
Observed sub-60 mV/dec slopes are not due to true negative capacitance.
Abstract
The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the framework of a FE polarization switching model. However, there is a large amount of literature attributing this effect to a stabilization of quasi-static (QS) negative capacitance (NC) in the FE. The technological implications of a stabilized non-switching (NS) QSNC model vs a FE switching model are vastly different; the latter precluding applications to sub-60 mV/dec SS scaled CMOS due to speed limitations and power dissipated in switching. In this letter, we provide a thorough analysis assessing the foundations of models of QSNC, identifying which specific assumptions (ansatz) may be unlikely or unphysical, and analyzing their applicability. We show that it…
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