LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection

TL;DR

LUT-Lock is a new LUT-based obfuscation method for FPGA and ASIC hardware that significantly increases resistance against SAT attacks by exponentially increasing solver execution time.

Contribution

The paper introduces LUT-Lock, a novel obfuscation algorithm that enhances security of FPGA and ASIC designs against SAT-based attacks.

Findings

LUT-Lock forces near exponential increase in SAT solver runtime.

Increasing the number of LUTs further prolongs attack execution time.

LUT-Lock improves hardware IP protection effectiveness.

Abstract

In this work, we propose LUT-Lock, a novel Look-Up-Table-based netlist obfuscation algorithm, for protecting the intellectual property that is mapped to an FPGA bitstream or an ASIC netlist. We, first, illustrate the effectiveness of several key features that make the LUT-based obfuscation more resilient against SAT attacks and then we embed the proposed key features into our proposed LUT-Lock algorithm. We illustrates that LUT-Lock maximizes the resiliency of the LUT-based obfuscation against SAT attacks by forcing a near exponential increase in the execution time of a SAT solver with respect to the number of obfuscated gates. Hence, by adopting LUT-Lock algorithm, SAT attack execution time could be made unreasonably long by increasing the number of utilized LUTs.