A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems
HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael A. Harding,, Onur Mutlu

TL;DR
This paper introduces a memory controller for hybrid DRAM-NVM systems that enhances performance and energy efficiency by intelligently caching heavily-reused, frequently-missed rows in DRAM based on row buffer locality and write patterns.
Contribution
It proposes a novel row buffer locality-aware caching policy that predicts and caches rows likely to incur frequent misses, optimizing data placement in hybrid memory systems.
Findings
Improved hybrid memory performance and energy efficiency.
Effective caching of high-reuse, high-miss rows in DRAM.
Reduced write latency impact by strategic data placement.
Abstract
Non-volatile memory (NVM) is a class of promising scalable memory technologies that can potentially offer higher capacity than DRAM at the same cost point. Unfortunately, the access latency and energy of NVM is often higher than those of DRAM, while the endurance of NVM is lower. Many DRAM-NVM hybrid memory systems use DRAM as a cache to NVM, to achieve the low access latency, low energy, and high endurance of DRAM, while taking advantage of the large capacity of NVM. A key question for a hybrid memory system is what data to cache in DRAM to best exploit the advantages of each technology while avoiding the disadvantages of each technology as much as possible. We propose a new memory controller design that improves hybrid memory performance and energy efficiency. We observe that both DRAM and NVM banks employ row buffers that act as a cache for the most recently accessed memory row.…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Data Storage Technologies · Advanced Memory and Neural Computing
