Estimating Latencies of Task Sequences in Multi-Core Automotive ECUs

TL;DR

This paper introduces a formal analysis technique to estimate end-to-end latencies of task sequences in multi-core automotive ECUs, supporting various activation patterns and using load assumptions for more accurate bounds.

Contribution

It presents the first formal approach utilizing load assumptions to exclude infeasible paths without relying on worst-case execution times.

Findings

Handles multi-core architectures and multiple activation patterns

Uses constraint programming to compute latency bounds

Excludes infeasible paths without worst-case execution times

Abstract

The computation of a cyber-physical system's reaction to a stimulus typically involves the execution of several tasks. The delay between stimulus and reaction thus depends on the interaction of these tasks and is subject to timing constraints. Such constraints exist for a number of reasons and range from possible impacts on customer experiences to safety requirements. We present a technique to determine end-to-end latencies of such task sequences. The technique is demonstrated on the example of electronic control units (ECUs) in automotive embedded real-time systems. Our approach is able to deal with multi-core architectures and supports four different activation patterns, including interrupts. It is the first formal analysis approach making use of load assumptions in order to exclude infeasible data propagation paths without the knowledge of worst-case execution times or worst-case response times. We employ a constraint programming solver to compute bounds on end-to-end latencies.