Fast inference of deep neural networks in FPGAs for particle physics

TL;DR

This paper demonstrates how FPGA hardware can efficiently perform neural network inference for particle physics applications, enabling low-latency, low-power real-time event processing at the LHC.

Contribution

It introduces hls4ml, a package based on High-Level Synthesis, to simplify FPGA implementation of neural networks for particle physics, with a case study on jet substructure classification.

Findings

Neural network inference in FPGAs can achieve ~100 ns latency.

The hls4ml package reduces firmware development time.

FPGA resources are sufficient for complex physics models.

Abstract

Recent results at the Large Hadron Collider (LHC) have pointed to enhanced physics capabilities through the improvement of the real-time event processing techniques. Machine learning methods are ubiquitous and have proven to be very powerful in LHC physics, and particle physics as a whole. However, exploration of the use of such techniques in low-latency, low-power FPGA hardware has only just begun. FPGA-based trigger and data acquisition (DAQ) systems have extremely low, sub-microsecond latency requirements that are unique to particle physics. We present a case study for neural network inference in FPGAs focusing on a classifier for jet substructure which would enable, among many other physics scenarios, searches for new dark sector particles and novel measurements of the Higgs boson. While we focus on a specific example, the lessons are far-reaching. We develop a package based on High-Level Synthesis (HLS) called hls4ml to build machine learning models in FPGAs. The use of HLS increases accessibility across a broad user community and allows for a drastic decrease in firmware development time. We map out FPGA resource usage and latency versus neural network hyperparameters to identify the problems in particle physics that would benefit from performing neural network inference with FPGAs. For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns.