Lightweight Hardware Architectures for Efficient Secure Hash Functions ECHO and Fugue

TL;DR

This paper introduces efficient fault detection schemes and reliable hardware architectures for the hash functions ECHO and Fugue, enhancing their security and performance with minimal overhead through ASIC implementation.

Contribution

It presents novel fault detection methods and hardware architectures for ECHO and Fugue, addressing reliability and security in cryptographic hardware.

Findings

High error detection coverage for hardware failures

Effective detection of malicious fault attacks

Acceptable hardware and timing overhead

Abstract

In cryptographic engineering, extensive attention has been devoted to ameliorating the performance and security of the algorithms within. Nonetheless, in the state-of-the-art, the approaches for increasing the reliability of the efficient hash functions ECHO and Fugue have not been presented to date. We propose efficient fault detection schemes by presenting closed formulations for the predicted signatures of different transformations in these algorithms. These signatures are derived to achieve low overhead for the specific transformations and can be tailored to include byte/word-wide predicted signatures. Through simulations, we show that the proposed fault detection schemes are highly-capable of detecting natural hardware failures and are capable of deteriorating the effectiveness of malicious fault attacks. The proposed reliable hardware architectures are implemented on the application-specific integrated circuit (ASIC) platform using a 65-nm standard technology to benchmark their hardware and timing characteristics. The results of our simulations and implementations show very high error coverage with acceptable overhead for the proposed schemes.