Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects
Roberto Ammendola, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro,, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli,, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Francesco Simula,, Piero Vicini

TL;DR
This paper discusses the design and evaluation of ExaNet, a scalable FPGA-based network architecture for the ExaNeSt and EuroExa projects, aiming to enable low power, high efficiency exascale computing systems.
Contribution
It introduces ExaNet, a novel FPGA-based network architecture, and reports on its design, testing, and preliminary performance metrics within the context of exascale computing projects.
Findings
Preliminary bandwidth and latency measurements are promising.
ExaNet supports various interconnection topologies and advanced routing.
The architecture enables application-specific acceleration and fault tolerance.
Abstract
The deployment of the next generation computing platform at ExaFlops scale requires to solve new technological challenges mainly related to the impressive number (up to 10^6) of compute elements required. This impacts on system power consumption, in terms of feasibility and costs, and on system scalability and computing efficiency. In this perspective analysis, exploration and evaluation of technologies characterized by low power, high efficiency and high degree of customization is strongly needed. Among the various European initiative targeting the design of ExaFlops system, ExaNeSt and EuroExa are EU-H2020 funded initiatives leveraging on high end MPSoC FPGAs. Last generation MPSoC FPGAs can be seen as non-mainstream but powerful HPC Exascale enabling components thanks to the integration of embedded multi-core, ARM-based low power CPUs and a huge number of hardware resources usable to…
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Taxonomy
TopicsInterconnection Networks and Systems · Cloud Computing and Resource Management · Software-Defined Networks and 5G
