A Survey of Techniques for Dynamic Branch Prediction

TL;DR

This survey reviews various dynamic branch prediction techniques, highlighting their classifications, challenges, and potential for future research to improve processor performance and energy efficiency.

Contribution

It provides a comprehensive classification and analysis of existing dynamic branch prediction methods, aiding researchers and designers in understanding current trends and gaps.

Findings

High accuracy in branch prediction improves processor performance.

Reducing latency and storage overhead remains a key challenge.

The survey identifies promising directions for future research.

Abstract

Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers and researchers.