Hardware design of LIF with Latency neuron model with memristive STDP synapses

TL;DR

This paper presents a hardware neuromorphic system combining a LIFL neuron model with memristive STDP synapses, enabling more information encoding and potential for complex neural network implementation.

Contribution

The paper introduces a CMOS-based LIFL neuron with memristive STDP synapses, enhancing information encoding and hardware integration for neuromorphic systems.

Findings

Simulation confirms system validity

Demonstrates potential for complex neural networks

LIFL neuron improves information encoding

Abstract

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks