New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata

TL;DR

This paper introduces novel symmetric and planar reversible full-adder/subtractor designs in Quantum-dot Cellular Automata, emphasizing minimal garbage outputs, fault tolerance, and improved efficiency over existing solutions.

Contribution

It presents a direct, optimal method for converting irreversible functions to reversible ones and proposes new fault-tolerant, symmetric, planar designs for full-adders and adders/subtractors in QCA.

Findings

Proposed designs outperform existing ones in area and delay.

New fault-tolerant five-input majority gate enhances reliability.

Reversible full-adder/subtractor circuits show reduced complexity and garbage outputs.

Abstract

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also, power dissipation is the main limitation of all the nano electronics design techniques including the QCA. Researchers have proposed the various mechanisms to limit this problem. Among them, reversible computing is considered as the reliable solution to lower the power dissipation. On the other hand, adders are fundamental circuits for most digital systems. In this paper, Innovation is divided to three sections. In the first section, a method for converting irreversible functions to a reversible one is presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. So, in this method, sub-optimal methods of using of conventional reversible blocks such as Toffoli and Fredkin are not used, having of minimum number of garbage outputs and so on. Then, Using the method, two new symmetric and planar designs of reversible full-adders are presented. In the second section, a new symmetric, planar and fault tolerant five-input majority gate is proposed. Based on the designed gate, a reversible full-adder are presented. Also, for this gate, a fault-tolerant analysis is proposed. And in the third section, three new 8-bit reversible full-adder/subtractors are designed based on full-adders/subtractors proposed in the second section. The results are indicative of the outperformance of the proposed designs in comparison to the best available ones in terms of area, complexity, delay, reversible/irreversible layout, and also in logic level in terms of garbage outputs, control inputs, number of majority and NOT gates.