B-DCGAN:Evaluation of Binarized DCGAN for FPGA

TL;DR

This paper introduces B-DCGAN, a binarized deep convolutional GAN optimized for FPGA implementation, demonstrating its feasibility and analyzing the trade-offs between reduced resource usage and data quality.

Contribution

The paper presents the design and FPGA implementation of B-DCGAN with binary weights and activations, and evaluates its performance and data quality impacts.

Findings

B-DCGAN reduces memory and circuit gate usage.

Implementation on Xilinx Zynq FPGA is feasible.

Data quality decreases with binarization and integer operations.

Abstract

We are trying to implement deep neural networks in the edge computing environment for real-world applications such as the IoT(Internet of Things), the FinTech etc., for the purpose of utilizing the significant achievement of Deep Learning in recent years. Especially, we now focus algorithm implementation on FPGA, because FPGA is one of the promising devices for low-cost and low-power implementation of the edge computer. In this work, we introduce Binary-DCGAN(B-DCGAN) - Deep Convolutional GAN model with binary weights and activations, and with using integer-valued operations in forward pass(train-time and run-time). And we show how to implement B-DCGAN on FPGA(Xilinx Zynq). Using the B-DCGAN, we do feasibility study of FPGA's characteristic and performance for Deep Learning. Because the binarization and using integer-valued operation reduce the memory capacity and the number of the circuit gates, it is very effective for FPGA implementation. On the other hand, the quality of generated data from the model will be decreased by these reductions. So we investigate the influence of these reductions.