The ESS FPGA Framework and its Application on the ESS LLRF System

TL;DR

This paper presents the ESS FPGA Framework designed to standardize and simplify FPGA development for the ESS LLRF system, enabling easier integration, configuration, and communication across different FPGA boards.

Contribution

The paper introduces a unified FPGA framework with automated tools and standardized interfaces, improving development efficiency and interoperability for ESS LLRF applications.

Findings

Framework successfully integrated LLRF control algorithms

Automated scripts streamline FPGA and software build processes

Enhanced modularity and extensibility of FPGA development

Abstract

The functions of the Low-Level Radio Frequency (LLRF) system at European Spallation Source (ESS) are implemented on different Field-Programmable Gate Array (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA) crate. Besides the algorithm, code that provides access to the peripherals connected to the FPGA is necessary. In order to provide a common platform for the FPGA developments at ESS - the ESS FPGA Framework has been designed. The framework facilitates the integration of different algorithms on different FPGA boards. Three functions are provided by the framework: (1) Communication interfaces to peripherals, e.g. Analog-to-Digital Converters (ADCs) and on-board memory, (2) Upstream communication with the control system over Peripheral Component Interconnect Express (PCIe), and (3) Configuration of the on-board peripherals. To keep the framework easily extensible by Intellectual Property (IP) blocks and to enable seamless integration with the Xilinx design tools, the Advanced eXtensible Interface version 4 (AXI4) bus is the chosen communication interconnect. Furthermore, scripts automatize the building of the FPGA configuration, software components and the documentation. The LLRF control algorithms have been successfully integrated into the framework.