A 1 GHz RF Trigger Unit implemented in FPGA logic

TL;DR

This paper presents a high-frequency 1 GHz FPGA-based Trigger Unit for CERN accelerators, utilizing internal serializer/deserializer circuitry for simplified timing and reconfigurability.

Contribution

The work demonstrates a nearly fully FPGA-embedded Trigger Unit operating at 1 GHz, enabling flexible reconfiguration and new operational modes.

Findings

Achieved 1 GHz operation within FPGA logic

Simplified timing constraints using internal serializer/deserializer

Enabled easy reconfiguration and mode development

Abstract

Applications of Trigger Units (TU) can be found in almost all accelerators at CERN. The requirements in terms of operating frequencies, configuration or modes of operation change from one application to another, how-ever, in terms of design requirements for the Trigger Unit, the operating frequency is probably the most demanding one. In this work, we present an implementation of a Trigger Unit almost fully embedded in the FPGA logic operating at a maximum frequency of 1 GHz using the internal serializer/deserializer circuitry to simplify the timing constraints of the design. This implementation allows easy reconfiguration of the module and the development of new modes of operation, which are described in this paper.