Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact

TL;DR

This paper introduces the first full-system simulator with integrated DRAM power-down modes, enabling detailed analysis of power-performance trade-offs across various workloads.

Contribution

We integrated DRAM power-down modes into gem5's controller model, creating a novel tool for comprehensive DRAM power analysis in full-system simulations.

Findings

Validated power-down functionality with sweep tests

Demonstrated model's utility with HPC workloads

Enabled detailed power-performance trade-off analysis

Abstract

Across applications, DRAM is a significant contributor to the overall system power, with the DRAM access energy per bit up to three orders of magnitude higher compared to on-chip memory accesses. To improve the power efficiency, DRAM technology incorporates multiple power-down modes, each with different trade-offs between achievable power savings and performance impact due to entry and exit delay requirements. Accurate modeling of these low power modes and entry and exit control is crucial to analyze the trade-offs across controller configurations and workloads with varied memory access characteristics. To address this, we integrate the power-down modes into the DRAM controller model in the open-source simulator gem5. This is the first publicly available full-system simulator with DRAM power-down modes, providing the research community a tool for DRAM power analysis for a breadth of use cases. We validate the power-down functionality with sweep tests, which trigger defined memory access characteristics. We further evaluate the model with real HPC workloads, illustrating the value of integrating low power functionality into a full system simulator.