# Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor

## TL;DR

This paper presents a novel, area-efficient out-of-order superscalar FPGA soft processor design based on the EDGE instruction set, demonstrating improved architecture feasibility and scheduler options.

## Contribution

It introduces a new approach to building high ILP EDGE soft processors with optimized microarchitecture and scheduler design for FPGA implementation.

## Key findings

- Feasibility of out-of-order FPGA architecture using EDGE
- Comparison of two scheduler design alternatives
- Enhanced area efficiency and performance potential

## Abstract

In-order scalar RISC architectures have been the dominant paradigm in FPGA soft processor design for twenty years. Prior out-of-order superscalar implementations have not exhibited competitive area or absolute performance. This paper describes a new way to build fast and area-efficient out-of-order superscalar soft processors by utilizing an Explicit Data Graph Execution (EDGE) instruction set architecture. By carefully mapping the EDGE microarchitecture, and in particular, its dataflow instruction scheduler, we demonstrate the feasibility of an out-of-order FPGA architecture. Two scheduler design alternatives are compared.