A Dual Approach to Scalable Verification of Deep Networks
Krishnamurthy (Dj) Dvijotham, Robert Stanforth, Sven Gowal, Timothy, Mann, Pushmeet Kohli

TL;DR
This paper introduces a scalable, general framework for verifying neural network properties by formulating the problem as an optimization task and providing anytime bounds, applicable to various architectures and specifications.
Contribution
It presents a novel verification approach that applies to general activation functions, uses Lagrangian relaxation, and offers anytime bounds with tightness guarantees.
Findings
Applicable to large and complex networks
Provides provable bounds on property violations
Demonstrates effectiveness on diverse verification tasks
Abstract
This paper addresses the problem of formally verifying desirable properties of neural networks, i.e., obtaining provable guarantees that neural networks satisfy specifications relating their inputs and outputs (robustness to bounded norm adversarial perturbations, for example). Most previous work on this topic was limited in its applicability by the size of the network, network architecture and the complexity of properties to be verified. In contrast, our framework applies to a general class of activation functions and specifications on neural network inputs and outputs. We formulate verification as an optimization problem (seeking to find the largest violation of the specification) and solve a Lagrangian relaxation of the optimization problem to obtain an upper bound on the worst case violation of the specification being verified. Our approach is anytime i.e. it can be stopped at any…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Code & Models
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdversarial Robustness in Machine Learning · Physical Unclonable Functions (PUFs) and Hardware Security · Integrated Circuits and Semiconductor Failure Analysis
