Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems
Song Chen, Jinglei Huang, Xiaodong Xu, and Qi Xu

TL;DR
This paper presents an integrated optimization framework for task partitioning, scheduling, and floorplanning on partially dynamically reconfigurable FPGAs, improving performance and resource utilization through a novel representation and search method.
Contribution
It introduces a partitioned sequence triple (P-ST) representation and a simulated annealing-based search for efficient co-optimization of partitioning, scheduling, and floorplanning.
Findings
Efficient O(n^2) computation of floorplanning and scheduling from P-ST.
Effective exploration of design space using simulated annealing.
Experimental results show improved optimization performance.
Abstract
Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfiguration (PDR) technology is anticipated to accelerate the reconfiguration process and alleviate the device shortage. In this paper, we propose an integrated optimization framework for task partitioning, scheduling and floorplanning on partially dynamically reconfigurable FPGAs. The partitions, schedule, and floorplan of the tasks are represented by the partitioned sequence triple P-ST (PS,QS,RS), where (PS,QS) is a hybrid nested sequence pair (HNSP) for representing the spatial and temporal partitions, as well as the floorplan, and RS is the partitioned dynamic configuration order of the tasks. The floorplanning and scheduling of task modules can be computed from the partitioned sequence triple P-ST in O(n^2)…
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