Impact of the domain structure in ferroelectric substrate on graphene conductance (authors' review)

TL;DR

This review discusses how the domain structure of ferroelectric substrates influences graphene conductance, analyzing theoretical models and their implications for device performance and miniaturization in nanoelectronics.

Contribution

It provides a comprehensive theoretical analysis of ferroelectric domain effects on graphene conductance, including hysteresis, p-n junctions, and size effects, with implications for device optimization.

Findings

Hysteresis memory effects in graphene FETs are influenced by absorbed dipoles and interface states.

Domain structures create p-n junctions affecting conductivity regimes from ballistic to diffusive.

Size effects and domain configurations can be exploited to improve device characteristics.

Abstract

Review is devoted to the recent theoretical studies of the impact of domain structure of ferroelectric substrate on graphene conductance. An analytical description of the hysteresis memory effect in a field effect transistor based on graphene-on-ferroelectric, taking into account absorbed dipole layers on the free surface of graphene and localized states on its interfaces is considered. The aspects of the recently developed theory of p-n junctions conductivity in a graphene channel on a ferroelectric substrate, which are created by a 180-degree ferroelectric domain structure, are analyzed, and cases of different current regimes from ballistic to diffusion one are considered. The influence of size effects in such systems and the possibility of using the results for improving the characteristics of field effect transistors with a graphene channel, non-volatile ferroelectric memory cells with random access, sensors, as well as for miniaturization of various devices of functional nanoelectronics are discussed.